1. Field of the Invention
The present invention relates to a lead frame used for a resin-sealed-type semiconductor device, a semiconductor device using the lead frame, and a method of manufacturing the semiconductor device.
2. Description of Related Art
A SiP (System in Package) technique having a plurality of semiconductor chips such as a memory or a CPU (central processing unit) mounted on one package has been developed.
FIG. 7 shows a side view of a semiconductor device having an SiP structure according to a prior art 1 (Japanese Unexamined Patent Application Publication No. 06-188280 (Sasaki et al.) FIGS. 1 and 3)). A semiconductor device 100 according to the prior art 1 includes an upper stage side semiconductor chip 101 flip-chip mounted on a surface of a plurality of inner lead parts 133 formed on one lead frame 130 and a lower stage side semiconductor chip 102 flip-chip mounted on a rear surface of the plurality of inner lead parts 133 as shown in FIG. 7. Then the upper stage side semiconductor chip 101 and the lower stage side semiconductor chip 102 are opposed to each other. In order to keep electrical isolation between the upper stage side semiconductor chip 101 and the lower stage side semiconductor chip 102, the inner lead parts electrically connected to the upper stage side semiconductor chip 101 and the inner lead parts electrically connected to the lower stage side semiconductor chip 102 are separated, and they are not commonly used. Sasaki et al. also discloses a structure in which electrode planes of two semiconductor chips are back-to-back opposed to each other contrary to the example of FIG. 7 and the semiconductor chips are electrically connected to the lead frame by wire bonding.
FIG. 8A shows a side view of a semiconductor device having an SiP structure according to a prior art 2 (Japanese Unexamined Patent Application Publication No. 11-330347 (FIGS. 7 and 8)) and FIG. 8B shows a partially enlarged perspective view of lead frames used for the semiconductor device. A semiconductor device 200 according to the prior art 2 is formed by separate two lead frames as shown in FIG. 8A. More specifically, an upper stage side semiconductor chip 101 is flip-chip mounted on a first lead frame 110 and a lower stage side semiconductor chip 102 is flip-chip mounted on a second lead frame 120. A first inner lead part 113 formed in the first lead frame 110 and a second inner lead part 123 formed in the second lead frame 120 form a laminated structure as shown in FIG. 8B. Further, an insulating layer 131 is interposed between the first inner lead part 113 and the second inner lead part 123 in order to keep electrical insulation.
FIG. 9A shows a top view of a semiconductor device having an SiP structure according to a prior art 3 (Japanese Unexamined Patent Application Publication No. 2004-342880 (FIG. 2)) and FIG. 9B shows a cross sectional view taken along the line IXB-IXB of FIG. 9A. As shown in FIGS. 9A and 9B, a semiconductor device 300 according to the prior art 3 includes an upper stage side semiconductor chip 101 and a lower stage side semiconductor chip 102 mounted by flip chip mount using three lead frames 130 (first lead frame 110, second lead frame 120, and third lead frame 140) having different steps.
In the semiconductor device 100 according to the prior art 1, two semiconductor chips are flip-chip mounted using one lead frame, as described above. Therefore, the flip chip mount of the upper stage side semiconductor chip 101 can be performed with the traditional technique. On the other hand, the flip chip mount of the lower stage side semiconductor chip 102 needs to be performed by inverting top and bottom direction of the lead frame 130 after mounting the upper stage side semiconductor chip 101. At this time, the upper stage side semiconductor chip 101 may be stressed or interfere with the stage. Even when the connection is made by wire bonding, the same problem may occur in the upper stage side semiconductor chip or the wire connected to the upper stage side semiconductor chip and the lead frame.
The semiconductor device 200 according to the prior art 2 employs the structure in which two lead frames are laminated in a vertical direction and the insulating layer 131 is interposed between a gap of the two lead frames, as shown in FIG. 8B. Therefore, there is caused a problem that the thickness of the package (Z direction in FIG. 8B) increases.
In the semiconductor device 300 according to the prior art 3, the first lead frame 110, the second lead frame 120, and the third lead frame 140 have different steps, which causes a problem that the thickness of the package (Z direction in FIG. 9B) increases.